Portable devices, such as mobile phones, digital cameras and music players, comprise non-volatile memory units. These portable devices have become smaller in recent years, as have the respective memory units. It is assumed that the miniaturization of portable devices will proceed. The amount of data that can be stored in the non-volatile memory unit may increase to improve the performance of the device. As a result, for example, more music songs, photos or other data can be stored in smaller devices.
Non-volatile memory units may be realized in different ways. Examples are read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM) and electrical erasable programmable read-only memory (EEPROM).
The advantage of the ROM is the low price per device. The ROM cannot be programmed electrically. Programming occurs during one of the production steps. Special masks that contain the data to be stored pattern the semiconductor device according to the data. When the production process has been completed, the content of the ROM can no longer be changed. Changes in data programming result in the expensive and time-consuming redesign of the special masks.
The PROM is manufactured as a blank memory. After having been programmed once, the content cannot be changed anymore.
The EPROM can be programmed again after having been exposed to ultraviolet light for erasing.
The above-described non-volatile memory unit cannot be electrically erased. The EEPROM can be electrically programmed and erased. It retains the stored data for a long time without power supply and can easily be programmed and erased many times.
The EEPROM comprises a plurality of memory cells for storing small pieces of information. There are memory cells for storing only one bit. Multi-bit memory cells, however, can store more than one bit. Means for storing a bit have two states. One state represents a logic zero. The other state represents a logic one.
An embodiment of a one-bit memory cell comprises a transistor body that includes a cell well having two doping areas. A channel region is located between the doping areas. A gate electrode is arranged above the channel region insulated by a dielectric layer that is arranged between the channel region and the gate electrode.
The cell well is formed by implanting ions into the substrate. The doping areas are formed by implanting ions in a further step. The type of the dopant ions used to form the doping areas differs from the type of the dopant ions used to form the cell well.
One of the doping areas serves as a source and the other one serves as a drain. A reading voltage is applied to the drain while the source is grounded. If the reading voltage exceeds a certain threshold voltage, a current flows. In accordance with the respective state, the threshold voltage varies. It is either higher or lower than the reading voltage. An alternative embodiment of a memory cell based on this structure is described below.
A non-volatile memory cell comprises a transistor as described above including a gate electrode arranged above a dielectric comprising a first oxide layer, a silicon nitride layer and a second oxide layer. The silicon nitride layer is used to trap electrons. Applying a positive gate voltage, electrons can tunnel from the substrate through the thin oxide layer, where they are subsequently trapped. The trapped negative charge increases the threshold voltage of the transistor. Likewise, the threshold voltage can be decreased by a negative voltage on the gate, removing the electrons from the nitride layer. When applying the reading voltage, a current either flows or not, depending on the threshold voltage. The two stages of the memory cell correspond to a switch that is either conductive or not.
A similar memory cell, however, also comprising a silicon nitride charge trapping layer between the channel region and the gate electrode, is able to store two bits. Such a cell is called nitride programmable read only memory (NROM) cell.
The nitride programmable read only memory (NROM) cell is described in U.S. Pat. No. 6,011,725 and Boaz Eitan et al.: “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000. Both of these references are incorporated herein by reference.
The oxide-nitride-oxide layer of the NROM cell comprises a nitride layer of the memory cell serving as a charge trapping layer sandwiched between the insulating oxide layers which avoid vertical retention. Two individual bits are stored in physically different regions of the even nitride layer. A first bit region is near a first doping area and a second bit region is near the second doping area. S. T. Kang et al.: “A Study of SONOS Nonvolatile Memory Cell Controlled Structurally by Localizing Charge-Trapping Layer,” Proceedings of IEEE Non-Volatile Memory Workshop, Monterey, 2003, which is incorporated herein by reference, describes a memory cell having two segregated ONO layers.
A memory cell array includes a plurality of memory cells arranged as a matrix having rows and columns. The rows of the cell array are arranged parallel to a first direction. The columns of the cell array are arranged parallel to a second direction that is orthogonal with respect to the first direction. The first and second doping areas of the memory cells in a column are aligned in a direction parallel to the second direction.
The gate electrodes arranged parallel to the first direction are connected to wordlines. A bitline connects the doping areas arranged parallel to the second direction. The bitline includes the sources and drains of the memory cells located on either side.
The bits are programmed by means of channel hot electron programming. Electrons are injected from the channel into the charge trapping region, according to the applied voltages. Programming of a first bit is performed by applying a programming voltage to the first doping area and the gate while grounding the second doping area. The electrons are injected and trapped in the first bit region, which is adjacent to the first doping area. Likewise, programming of a second bit is performed by applying a programming voltage to the second doping area and the gate while grounding the first doping area. The electrons are injected and trapped in the second bit region.
For erasing a bit, hot holes or Fowler-Nordheim tunneling can be used. Erasing of the first bit is performed by applying erasing voltages to the gate or to the first doping area and the gate resulting in a lateral field. Holes are caused to flow through the bottom oxide layer for compensating the charge of the electrons.
A bit information is read by applying a reverse voltage between the first and second doping area compared to the programming voltage that is used to program the bit. Relatively small charges near the grounded one of the first and second doping areas prevent or reduce current flow. For example, reading of the first bit is performed by applying reading voltages to the second doping area and the gate. The first doping area is grounded. The current flows, while there are no trapped charges inside the first bit region. While there are trapped charges inside the first bit region, the current flow is reduced or the current does not flow.
The first and second bit of each memory cell can be programmed, read and erased by applying the programming, reading and erasing voltage respectively to the adjusted combination of the bitlines and the wordline, which are connected with the respective memory cell.
A conventional NROM cell as described above comprises an even oxide-nitride-oxide layer beneath the gate having two different regions for storing the charges representing the first and second bit information. As a result, the injection of electrons or holes for changing one bit information can influence the other bit. The influence of residual charges in a region of the nitride layer located adjacent to the bitline may be negligible. An unintended injection into the nitride layer of state-of-the-art NROM cells above the channel region cannot be avoided.
The local distribution of electrons in the charge trapping region is wider than for holes, because the mobility of electrons and holes in nitride differs. Holes are much more mobile. The same number of holes is spread in a wider area than the corresponding number of electrons. There is not a hole adjacent to each electron compensating its charge. More widely spread holes than electrons are used to cover the charge of the electrons. In order to change a bit information that is represented by electrons, more holes are injected to compensate the charge of the electrons. During a further programming step, more electrons may be injected into the charge trapping region again, requiring more holes to compensate the charge during the following erase cycle. This aging process results in an increase of the erasing voltages and the programming and erasing processes take more time.
The enhanced mobility of the holes representing one bit influences the charges representing the other bit and result in a retention loss.